Static random access memory (SRAM) is a common type of random access memory used aboard integrated circuit chips. SRAM is used in many applications, including cache memory for general purpose microprocessors, on-board memory for system-on-chip devices and on-board memory for application specific integrated circuits, among others. For many years the design of individual SRAM cells, e.g., four device and six device cells, has included the concept of designing the output device(s) and pull-down device(s) within each cell so that they satisfy a predetermined beta ratio constraint. As is well known in the art, for a transistor β=γ (W/L), where γ is the transconductance and W and L are, respectively, the width and length of the transistor channel. Conventionally, SRAM designers strive to keep the ratio between the β value of each output device and the β value of the corresponding pull-down device, i.e., beta ratio, between about 1.5 and about 2.0. Experience with SRAM made using current-and previous-generation integration scales and operating voltages has shown that limiting the beta ratio in this manner generally results in stable SRAM cell, i.e., an SRAM cell that is resistant to read disturbances and other types of instability.
Generally, satisfying the beta ratio constraint when designing SRAM cells made using current-and previous-generation integration scales has been sufficient. This is so because the geometric tracking between transistors within SRAM cells has been adequate, specifically, the widths and lengths of the diffusion source/drain regions have been adequately matched to provide good electrical stability and Vdd has been high enough (typically 1.5V or more) to provide sufficient overdrive to compensate for minor geometrical imbalances. However, in the next generation and follow-on generations of integration scale and operating voltages, future SRAM will generally be less tolerant to manufacturing limitations that tend to cause read disturbances and other instabilities.
This is particularly true at the present time when conventional photolithography techniques are being stretched to their limits in order to produce ever smaller feature sizes. For example, FIG. 1A shows an as-designed output transistor 10 and corresponding pull-down transistor 14 as they should appear in an integrated circuit. The pair of transistors 10, 14 includes three diffusion source/drain regions 18A-C and corresponding respective gates 22, 26. It is readily seen in FIG. 1A that diffusion source/drain regions 18A-B on either sides of gate 22 have a width 30 that is approximately one-half the width 34 of diffusion source/drain regions 18B-C on either side of gate 26. Correspondingly, note the well-defined notch 38 that is formed in diffusion source/drain region 18B between gates 22, 26. In addition, note the locations of notch 38, which is precisely centered between gates 22, 26. The difference in widths 30, 34 contributes to the beta ratio being a value other than 1, in this case about 2.0, in order to satisfy the conventional beta ratio constraint discussed above. In the present example, it is noted that width 34 is about twice width 30 yielding a beta ratio of about 2.0. This is so because the lengths of the diffusion source/drain regions 18A-C are identical and gates 22, 26 are precisely centered between the corresponding respective diffusion source/drain regions. It is noted that in other examples the lengths of diffusion source/drain regions 18A-C beneath the respective gates 22, 26 could also, or alternatively, be different so as to affect the beta ratio.
In contrast, FIG. 1B illustrates output and pull-down transistors 10′, 14′ as manufactured using conventional photolithography techniques. In comparing and contrasting FIGS. 1A and 1B, it is readily seen in FIG. 1B that the as-manufactured transistors 10′, 14′ include a number of deviations from as-designed transistors 10, 14 of FIG. 1A. These deviations are due to physical limitations of various steps of the manufacturing process, such as imprecision in the creation of the photolithography masks, imprecision in the deposition and etching steps, and imprecision in mask alignment, and undesirable effects of the behavior of light and diffusion particles as they pass through the openings in the masks. For example, as-manufactured “notch” 38′ of FIG. 1B is blurred and much less distinct than as-designed notch 38 of FIG. 1A. In addition, as-manufactured gates 22′, 26′ and diffusion source/drain regions 18A′-C′ of FIG. 1B do not have the sharp corners of the corresponding as-designed gates 22, 26 and diffusion source/drain regions 18A-C of FIG. 1A. Nor are as-manufactured gates 22′, 26′ of FIG. 1B located as precisely relative to diffusion source/drain regions 18A′-C′ as as-designed gates 30, 34 of FIG. 1A are located relative to diffusion source/drain regions 18A-C.
Due to the various manufacturing limitations, as-manufactured devices, such as as-manufactured devices 10′, 14′ of FIG. 1B, deviate from as-designed devices, such as as-designed devices 10, 14 of FIG. 1A, in their physical dimensions and locations, which translates into deviations in operating characteristics. Relative to the beta ratio constraint discussed above, deviations of the as-manufactured channel widths and lengths will cause the β values for the manufactured devices to deviate from their as-designed values. Under present manufacturing trends, as feature sizes become smaller, the magnitudes of the β value deviations will increase, and the deviations themselves will be more influenced by the manufacturing limitations. This greater influence of manufacturing limitations will result in more unpredictability in terms of SRAM stability and, consequently, more conservative SRAM designs that will likely lag optimal designs of other integrated circuitry, such as logic circuitry.
Compounding the larger magnitudes and variability of β-value deviations is the fact that SRAM operating voltages will continue to decrease with increasing integration scale and corresponding decreasing feature sizes. As mentioned above, in conventional SRAM, the SRAM driving voltages are typically 1.5V and greater, and the corresponding transistor threshold voltage (Vt) is on the order of 300 mV. Consequently, there is much headroom for overdriving conventional devices with a 1.5V Vdd in order to overcome deviations in the as-manufactured β values resulting from manufacturing limitations. However, in the next generation of SRAM, operating voltages will likely be on the order of IV or less and the threshold voltage will likely be on the order of, e.g., 200 mV, leaving much less headroom for providing device overdrive. Consequently, what is needed is SRAM having stability that is relatively highly predictable regardless of feature size, technology used to manufacture the SRAM and operating voltage.